The present invention relates in general to a nonvolatile semiconductor for use as a memory device and to a method for producing the same, and, in particular, to a technique which is useful for achieving an increase in the memory capacity of flash memories.
As a memory wherein data can be erased at a time, among nonvolatile semiconductor memories wherein data can be electrically rewritten, the so-called flash memory is known. The flash memory has excellent portability and impact resistance, and data memorized therein can be electrically erased at a time. In recent years, therefore, the demand for the flash memory has been expanding rapidly as a memory device for use in small-sized portable information-processing instruments, such as portable personal computers and digital still cameras. However, in order to expand the market thereof, it is important to make the area of the memory cells smaller, thereby decreasing the cost per bit.
Japanese Patent No. 2694618 describes a flash memory having imaginary-grounding type memory cells, each using three-layer polysilicon gates. Each of the memory cells described in this document is composed of a semiconductor region, which is formed in a well in a semiconductor substrate, and three gate electrodes. The three gates are a floating gate formed over the well, a control gate formed to extend over both the well and the floating gate, and an erasing gate formed between the control gate, a control gate adjacent thereto and the floating gate. The three gate electrodes are each made of polysilicon, and they are separated from each other through an insulator film. The floating gate and the well are also separated from each other through an insulator film. The control gates of plural memory cells are connected to each other in the row direction so as to constitute a word line. Source and drain diffusion layers of the memory cells are formed in the column direction, and any one of the diffusion layers is commonly used between memory cells that are disposed adjacent to each other. Thus, the memory cells turn into an imaginary grounding type. As a result, the pitch thereof in the column direction is small. Each of the erasing gates is arranged in parallel to each channel, and also in parallel to the word lines (control gates), between the word lines.
When data is written in a selected one of the memory cells, independent positive voltages are applied to the word line and the drain thereof, and further voltages at the well, the source and the erasing gate thereof are set to 0 V. In this way, hot electrons are generated in the channel region near the drain, and then the electrons are injected into the floating gate so that the threshold value of the selected memory cell rises. When data is erased, a positive voltage is applied to the erasing gate, and further voltages at the word line, the source, the drain and the well are set to 0 V. In this way, electrons are discharged from the floating gate to the erasing gate so that the threshold value lowers.
Japanese Unexamined Patent Publication No. 2002-373948 discloses a flash memory equipped with split gate type memory cells having an AND mode array structure. In each of the memory cells described in this document, a trench is made in a substrate; an auxiliary gate is buried in the trench; and a diffusion layer, which becomes a data line, and the channel region of the auxiliary gate are formed on the bottom face and the side faces of the trench. In this way, the pitch of the memory cells in the data line direction is small.
Japanese Unexamined Patent Publication No. 2001-156275 discloses a nonvolatile semiconductor memory having memory cells each using three-layer polysilicon gates. In each of the memory cells described in this document, a third gate electrode, which is different from a floating gate and a control gate, is extended in the data line direction of the memory. A reversion layer formed in the substrate, when the channel under the third gate electrode is turned on, is used as a data line. This makes it possible to delete any diffusion layer in the memory array. Consequently, the pitch of the data lines can be small.